Cadence Design Systems announced that its digital tools and advanced IC packaging solutions support the new TSMC InFO_MS (InFO with Memory on Substrate) packaging technology.
Image: Cadence is providing support for TSMC InFO_MS advanced packaging technologies. Photo: courtesy of Maicyber / FreeDigitalPhotos.net.
Support for this TSMC packaging technology enables mutual customers to create new, complex chips using 3D stacking techniques to bring innovative new products to market much faster than ever before.
Cadence has made improvements to its existing InFO flow to support the new InFO_MS packaging technology, providing a flexible suite of advanced packaging solutions to customers designing chips of various sizes and levels of complexity with memory integrated on InFO.
The Cadence signoff and packaging solutions incorporate several capabilities to advance the adoption of TSMC’s InFO_MS packaging technology.
The Cadence tools in the flow include the Quantus Extraction Solution, Voltus-Sigrity Package Analysis solution, Tempus Timing Signoff Solution, Physical Verification System (PVS), OrbitIO interconnect designer, Cadence System-in-Package (SiP) Layout enhancements and Sigrity PowerSI technology, Sigrity PowerSI 3D-EM Extraction Option, Sigrity PowerDC technology, Sigrity XtractIM™ technology and Sigrity SystemSI™ technology.
Cadence Custom IC & PCB Group general manager and senior vice president Tom Beckley said: “Cadence has continued to partner with TSMC to deliver new capabilities in support of its advanced packaging technologies that allow customers to deliver innovative designs more efficiently.
“The new InFO_MS solution can empower our mutual customers to utilize the latest packaging techniques when creating complex designs, and we are committed to enabling them to achieve their design objectives using our tools, flows and methodologies.”
“The collaboration with Cadence on the InFO_MS design flow enriches our established InFO, WoW and CoWoS chip integration solutions, giving customers more flexibility to incorporate multiple die integration using 3D stacking techniques,” said Suk Lee, TSMC senior director, design infrastructure marketing division.
“Our ongoing collaboration with Cadence is enabling customers to use our packaging technologies effectively so they can reduce design schedules and achieve aggressive design goals.”
Source: Company Press Release